////////////////////////////////////////////////////////////////////////////////
//
// The University of Illinois/NCSA
// Open Source License (NCSA)
//
// Copyright (c) 2014-2020, Advanced Micro Devices, Inc. All rights reserved.
//
// Developed by:
//
//                 AMD Research and AMD HSA Software Development
//
//                 Advanced Micro Devices, Inc.
//
//                 www.amd.com
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to
// deal with the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
//  - Redistributions of source code must retain the above copyright notice,
//    this list of conditions and the following disclaimers.
//  - Redistributions in binary form must reproduce the above copyright
//    notice, this list of conditions and the following disclaimers in
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//  - Neither the names of Advanced Micro Devices, Inc,
//    nor the names of its contributors may be used to endorse or promote
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////////////////////////////////////////////////////////////////////////////////

#include "core/inc/queue.h"
#include "core/inc/runtime.h"

namespace rocr {
namespace core {

// HSA Queue ID - used to bind a unique ID
std::atomic<uint64_t> Queue::hsa_queue_counter_(0);

void Queue::DefaultErrorHandler(hsa_status_t status, hsa_queue_t* source, void* data) {
  if (core::Runtime::runtime_singleton_->flag().enable_queue_fault_message()) {
    const char* msg = "UNKNOWN ERROR";
    HSA::hsa_status_string(status, &msg);
    fprintf(stderr, "Queue at %p inactivated due to async error:\n\t%s\n", source, msg);
    abort();
  }
}

}  // namespace core
}  // namespace rocr
